Non-volatile memory (NVM) devices generally include an array of NVM cells arranged into rows and columns. Each memory cell may have a gate, a source and a drain, where the gate controls current flow between the source and the drain. The amount of current flow generally depends on the gate voltage magnitude, the drain-source voltage, and a threshold voltage of the memory cell, where the threshold voltage is adjusted depending on the state of the memory cell. Usually, a high threshold voltage a low cell current define a Programmed State in the memory cell, and a low threshold voltage and a high cell current define an Erased State in the memory cell.
The NVM cell array is usually arranged so that cells in a same row are interconnected by a word line connecting the gate of each cell, and cells in a same column are interconnected by two bit lines, one connecting to the source of each cell and one connecting to the drain of each. The memory cell array may include a virtual ground architecture (VGA) wherein two neighboring cells in a same row may share a same bit line, and where the bit line for one cell may serve as a source bit line while for the neighboring cell it may serve as a drain bit line. Examples of VGA architectures are described in U.S. Pat. No. 5,650,959; U.S. Pat. No. 6,130,452; and U.S. Pat. No. 6,175,519; all of which are incorporated herein by reference in their entirety.
The memory cells in NVM devices may be configured to store more than one bit, for example two bits. A first bit is typically stored on one side of the memory cell and the second bit is stored on the other side of the same memory cell. Reading of each bit is executed by applying a source voltage to the side of the memory cell where the bit is located and a drain voltage to the opposite side of the cell. In addition, each side of the memory cell can store more than one bit, for example, two bits. Storing of more than one bit may be achieved by adjusting the magnitude of the programming voltage and the threshold voltage of the memory cell. The state of these bits may be determined during a read operation by sensing the current drawn by the memory cell while a read voltage is applied to the gate.
One technique used to determine the state of the bits includes “drain-side” sensing which includes connecting the drain to a sensing circuit and connecting the source to ground. A current drawn by the cell (flowing into the drain) from the sensing circuit is compared by the sensing circuit to a reference “read” current to allow the state of the read bit to be determined. For example, if the current drawn by the cell is greater than the reference read current, then the bit being read may be considered to be in the erased state while if the current drawn is less than the reference read current, the bit may be considered to be in the programmed state. Alternatively to using the drain-side sensing technique, the state of the bits in the cell may be determined using “source-side” sensing, where the sensing circuit is connected to the source and the current flowing out of the source is measured by the sensing circuit and compared to the reference read current.
In memory cell arrays with virtual ground architecture, the reliability of the above-mentioned sensing techniques may be increased by introducing a “read” margin which is associated with the reference read current. In such cases, a “sensed” current (flowing into the drain or out of the source) must be greater or lesser than the reference read current by the read margin in order to positively establish the state of the bits. For example, if the sensed current exceeds the reference read current by a value which may be equal to or greater than the read margin, the bit may be considered as erased, and if it is less than the reference read current by a value equal to or greater than the read margin, the bit may be considered as programmed. This may prevent incorrectly reading bits due to conditions typically known as “neighbor effect”, or “pipe” effect, wherein the sensed current flowing through the cell may be affected by leakage currents (“pipe” currents) flowing though neighboring memory cells.
Pipe currents are generally created as a result of a difference between the drain/source voltage level of the cell that is being read and the drain/source voltage level across one or more neighboring cells which are not being read. The pipe current can either increase or reduce the sensed current, and thus change the apparent logical value of the bits in the read memory cell. The size of the pipe current may depend on the neighboring cell's operating condition and which may include, for example, whether it is in an erased or programmed state, temperature, applied gate voltage, parasitic capacitance between bit lines, and transient response of the memory cell.
Known devices and/or methods attempt to deal with the problem of pipe currents and accurate reading of “sensed” current in memory cells, some of which are mentioned below.
US 2008/0013379 to Lin et al., relates to “a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.”
US 2010/0238746 to Chen, relates to “a reading circuit in a memory, having a first memory cell coupled to a first bit line and a second bit line, a second memory cell coupled to the second bit line and a third bit line and a third memory cell coupled to the third bit line and a fourth bit line, is provided. The reading circuitry includes a sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line to the drain side bias circuit to receive the drain side bias in a read operation mode. The second selection circuit connects the first bit line and the fourth bit line to the sensing circuit in the read operation mode, so that the sensing circuit senses a current of the first memory cell.”
U.S. Pat. No. 6,731,542 to Le et al., relates to “a memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.”
U.S. Pat. No. 6,744,674 to Le et al. relates to “a memory circuit senses current in a target cell during a read operation. According to one exemplary embodiment, the memory circuit comprises the target cell, a first neighboring cell, and an operational amplifier. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a drain voltage. A sensing circuit is coupled at a first node to at least one of the first bit line or the second bit line. The first neighboring cell has a third bit line connected to a second node. The operational amplifier has an output terminal connected at the second node to the third bit line. The operational amplifier has a noninverting input terminal connected to said first node, and also has an inverting input terminal connected to the second node.”